the STM32 OTG core seems to be provided by DWC. At position 0x40 in the register maps is the GSNPSID core revision. In diferent STM32s I have seen revisions from 2 72a up to 3.20a. Different versions of the OTG core need to be initialized different, and the STCube file use the GSNPSID register internally.
Please define the GSNPSID register in the system headers.