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STM32F3 opamp in PGA mode: DC conditions

Question asked by frackers on Feb 27, 2017



I'm trying to determine how I set the DC conditions (i.e. input bias) on the +ve input of an opamp on the STM32F3 series when all the feedback is internal during PGA mode. If I set the input to half way between the rails and set the gain at 4, the output immediately slams across to the VDD line (pretty much as expected!!).


Should I be using connected mode with the inverting input enabled and put that to the mid point of the supply and then AC couple into the +ve input pin via a capacitor?


I'm a bit lost where half my components are inside the SOC!