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L6470 - Vdd Vreg Vs caps, SW input pin voltage

Question asked by iurie on Mar 20, 2012
Latest reply on Mar 22, 2012 by Enrico Poli
Hi! 
I have some questions about L6470 decoupling and voltage tolerance.
1. If I use an external 3.3v to drive both Vreg and Vdd (internal reg disabled), do I still need a 40uf Vreg cap or I can use just one 10uf?
2. Can I use Vs bulk capacitor with lover value but better ESR? ESR and Ripple current is primary parameters for Vs bulk cap, am I right?
3. Is the SW pin still 5v tolerant when external Vreg = Vdd = 3.3v?
Thanks, Iurie

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