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Bad  GPIO_BRR_BRx definitions in V2.6.0 STM32Cube_FW_F4_V1.14.0 headers

Question asked by Uwe Bonnes on Feb 24, 2017

Hello,

 

as L1/F2/F7, Stm32F4 has no explicit Gpio Bit Reset register. To reset a Gpio bit , the bit in the uppper halfword of BSRR has to be set.

 

In some recent Cube update, definition like

#define GPIO_BRR_BR0_Pos (0U)
#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk

in stm32f405xx.h were introduced.

At the moment these definitions are missleading. Either make position GPIO_BRR_BR0_Pos (16U) or better remove these definitions.

 

Bye

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