Gerry Briggs

Register Settings for PWM on an STM8L

Discussion created by Gerry Briggs on Feb 23, 2017
Latest reply on Feb 27, 2017 by Maxime TEISSIER

There are many many registers that must be set in order to have a PWM output based on either TMR2 or TMR3.  I will talk about each, to the extent that I understand them, using the STM8L051F3 as the example:

 

PB_DDR:   bits 0, 1, and 2 must be set so that the micro pins are configured as outputs

PD_DDR:   bit 0 must be set so that Port D.0 is an output.  Now all 4 channels, 2 of TIM2 and 2 of TIM3 now outputs

PB_CR1 and PB_CR2: bits 0, 1 and 2 are set so that you dont need a pull-up resistor on the output

PD_CR1 and PD_CR2: bit 0 is set for same reason as above

 

CLK_PCKENR1:   bits 0 and 1 must be set simply so that the master clock feeds the TIM2 and TIM3 circuits

 

Now just concentrating on Timer 2, since Timer 3 is the same but use TIM3 instead of TIM2 as register nameheads for TIM3

 

TIM2_PSCR:  bits 0, 1, and 2 control the prescaler of the clock frequency, which can be divided by up to 128

 

TIM2_ARRH and TIM2_ARRL:   these 16 bits control the auto-reload (when the clock reaches this point it goes back to 0)

TIM2_CCR1H and TIM2_CCR1L:   these 16 bits control the duty cycle for channel 1 of timer 2 (must be lower than ARRH)

TIM2_CCR2H and TIM2_CCR2L:   these 16 bits control the duty cycle for channel 2 of timer 2 (must be lower than ARRH)

 

         Theoretically, TIM2 clock counts up, once it reaches TIM2_CCR1H:TIM2_CCR1L, channel 1 output switches polarity

         When the clock finally reaches TIM2_ARRH:TIM2_ARRL, channel 1 output switches polarity back and starts over

 

TIM2_CR1:   set bit 0 to enable the actual counter TIM2

TIM2_BKR:   set bit 7 to enable the PWM to the pin, overriding what you had set on PB_ODR and PD_ODR for those pins

 

TIM2_CCER1:   set bit 0 to enable channel 1 and set bit 4 to enable channel 2.  Bits 1 and 5 determine polarity of each

TIM2_CCMR1:   set bits 6 and 5 so that TIM2 is running in PWM mode.  Bit 4 determines which of two types of PWM mode set bit 3 since the datasheet says "For correct operation, preload registers must be enabled when the timer is in PWM mode."  Clear bits 1 and 0 to ensure the timer is in OUTPUT MODE

 

TIM2_EGR:   set bit 0 of this so that the shadow registers load into the correct places ?  I read this somewhere

 

 

Unfortunately, even after dealing with all these registers, it seems impossible to activate the PWM correctly.  I know the counter is on and working since I have an infinite loop that sends the upper 4 bits of TIM2_CNTRH to the upper 4 bits of PB_ODR.

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