Our application on the SPC560P44L3 switches to HALT0 mode in the idle loop for power saving. The PIT is configured to wakeup the CPU every msec for handling timers, which works just fine.
Now I'd like to configure the free running STM for highres time keeping, but it seems that during HALT0 state the STM counter does not increment.
Unfortunately I'm not able to provide a small test program, as the logic for event handling, timers and power saving is scattered throughout the project. Basically what I do to reproduce this is:
- Program the PIT for 1Khz timer interrupts
- Read STM timer -> t1
- Wait for interrupts by doing SetRunMode(SPC5_RUNMODE_HALT0)
- Read STM timer -> t2
System clock is set to 16MHz, STM divider to 1, so I'd expect (t2-t1) to be 16e6/1000 = 16e3. Instead, the number is much smaller and varies. If however I change the line with SetRunMode() to asm("wait"), the results are exactly as expected.
HALT0 mode is configured like this:
#define SPC5_ME_HALT0_MC_BITS (0UL | SPC5_ME_MC_MVRON | SPC5_ME_MC_DFLAON_LP | SPC5_ME_MC_CFLAON_LP | SPC5_ME_MC_IRCON | SPC5_ME_MC_PLL0ON | SPC5_ME_MC_XOSC0ON | SPC5_ME_MC_IRCON | SPC5_ME_MC_SYSCLK_FMPLL0)
I'm probably missing something in the datasheet about clock gating to the STM, but I'm not able to find a ME_PCTLx register which gates the STM clock.
Any hints much appreciated,