If the master sends the adress , but doesn't send the last clk pulse to receive the ACK from the slave, the slave will not release the SDA line.
The problem is, that the ADDR-Flag only gets set AFTER the ACK was sent. If that clock pulse got lost due to an error, the slave will keep the SDA line low and not trigger any interrupt.
As far as I've investigated, there is no way to find out that the STM32 is pulling the SDA line low, if a pulse gets lost during adress reception. (Slave can't pull it all the way to low, because of another resistor in line to see if slave or master pulls line down)
The master already resets himself via a timeout, but the slave doesn't, as there is no interrupt triggered. Is there a way to fix this somehow else besides blind software resetting of the I2C periphal if it doesn't receive any data for 2ms?
(There are multiple I2C devices in the system, which get new data every 2ms.)
The only flag set in the I2C-slave was the busy bit.
Maybe there is a way to find out that the Adress matched, but the ACK is not sent yet? That would be perfect in this case, as I could reset it superfast if there is no more clk pulse.
This one shows a pin triggered by the ADDR-Interrupt (yellow), as you can see, the interrupt gets triggered right after clk-pulse 9.
When just looking at it it seems like the master notices that the clk was not sent correctly (first image), as it tries to send the last bit again? The adress byte is supposed to be 0b01010010. If the master took all the clk pulses as valid (even the little one), this one would be 0b01010011. Nevertheless, the slave problem needs to get solved itself, as it could crash the bus.