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STM32F437 clock problem.

Question asked by John Hite on Feb 3, 2017
Latest reply on Feb 3, 2017 by John Hite

I have my clock setup for 168MHz and I see that with a scope at MD0. But a call to BSP_CPU_ClkFreq() indicates it is running at 550 MHz. This is the setup I have in bsp.c:

 

//  Configure for 8MHz XTAL => 168MHz SysClk
#define  BSP_BIT_RCC_PLLCFGR_PLLM                4u
#define  BSP_BIT_RCC_PLLCFGR_PLLN              168u
#define  BSP_BIT_RCC_PLLCFGR_PLLP                2u
#define  BSP_BIT_RCC_PLLCFGR_PLLQ                7u
  RCC_DeInit();
  RCC_HSEConfig(RCC_HSE_ON);                /* HSE = 8MHz ext. crystal.                            */
  RCC_WaitForHSEStartUp();

 

  RCC_HCLKConfig(RCC_SYSCLK_Div1);          /* HCLK    = AHBCLK  = PLL / AHBPRES(1) = 168MHz.       */
  RCC_PCLK2Config(RCC_HCLK_Div2);           /* APB2CLK = AHBCLK  / APB2DIV(2)       = 84MHz.        */
  RCC_PCLK1Config(RCC_HCLK_Div4);           /* APB1CLK = AHBCLK  / APB1DIV(4)       = 42MHz (max).  */

 

                                            /* PLLCLK    = HSE * (PLLN / PLLM)      = 336MHz.    */
                                            /* SYSCLK    = PLLCLK / PLLP            = 168MHz.       */
                                            /* OTG_FSCLK = PLLCLK / PLLQ            =  48MHz.   */


  RCC_PLLConfig(RCC_PLLCFGR_PLLSRC_HSE,
                BSP_BIT_RCC_PLLCFGR_PLLM,
                BSP_BIT_RCC_PLLCFGR_PLLN,
                BSP_BIT_RCC_PLLCFGR_PLLP,
                BSP_BIT_RCC_PLLCFGR_PLLQ);

 

  RCC_PLLCmd(ENABLE);

 

  while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET) {  /* Wait for PLL to lock.                                */
      ;
  }

 

  FLASH_SetLatency(FLASH_Latency_5);                     /* 5 Flash wait states when HCLK > 120MHz.              */
  FLASH_PrefetchBufferCmd(ENABLE);

 

  RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);             /* HCLK = SYSCLK = PLL = 168MHz.                        */
  while (RCC_GetSYSCLKSource() != RCC_CFGR_SWS_PLL) {
      ;
  }

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