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STM32F3: Specifics of using DBG pins for GPIO

Question asked by artes.benjamin on Jan 30, 2017
Latest reply on Jan 30, 2017 by waclawek.jan

I'm using a 64-pin STM32F303 in a design and looking into using some of the SW Debug Pins for LEDs.  I've read through the Reference and Programming Manuals and Datasheets for details but am a little confused on some of the specifics and would like some clarification.


How I believe re-assignment of DBG pins as GPIOs works:

  • On Reset all JTAG and SW pins are configured as their Alternate Function Debug mode.  The JTAG Debug Port (DP) is active.  Any attempts to change the configuration of the JTAG pins will be ignored (with the exception of SWO which, depending on TRACE setting of DBGMCU->CR, may have it's configuration changed).
  • Firmware can disable JTAG and SW by calling...?  I see examples of changing the AFIO->MAPR register on other STM32 processors but can't seem to find an equivalent for the STM32F3.
    • Once JTAG and SW are disabled, attempts to connect with a debugger will fail unless the debugger connected with nRST and resets the MCU.
  • If the debugger negotiates a change to SW-DP then all JTAG pins except, now, SWDIO and SWCLK (and potentially SWO), can be re-configured as usual.
    • Is there a way to check what DP is currently selected (so that we can look to see if SW is selected and know that the debugger is connected and not bother trying to re-configure the associated pins)?