I've read several forums regarding the potential ethernet instability by supplying the clock for an RMII Ethernet PHY chip from MCO of an STM32F4. This is one in particular stood out http://www.chibios.com/forum/viewtopic.php?f=3&t=23&start=150. I have also seen this topic discussed in this ST community forum.
My next project is to develop a custom board for the STM32F746VGT6 with an ethernet PHY chip (LAN8742A). The STM32F746G-DISCO PHY chip (LAN8742A) shares the same clock as the F7 (NZ2520SB-25.00M) at 25 MHz. So i thought this might be the best approach for the F7. However, i have seen the F7 used with a similar PHY chip (LAN8720A) in RMII with the clock supplied by MCO.
What is the go-to design approach for ethernet data stability/reliability/low jitter? I am also looking to add USB to the board and will need to meet the clock requirements to run both USB and Ethernet simultaneously.
Thanks in advance.