In synchronous mode, USART_CR2.LBCL allows to omit the clock pulse associated with last data bit.
The text in "USART synchronous mode" chapter hints that
Depending on the state of the LBCL bit in the USART_CR2 register clock pulses will or will not be generated during the last valid data bit (address mark).
but I am none the wiser.
I am untouched with the old-school synchronous serial interfaces, so I probably miss some important context.