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Im working for bootloader on SPC564A80B4. Facing issues in system clock generation

Question asked by Chamaraja.Mahesh on Jan 22, 2017
Latest reply on Mar 14, 2017 by Chamaraja.Mahesh

Hello,  I configured in enhanced mode for system clock generation, our input clock is 40Mhz external crystal and need to generate 150Mhz  system clock. Since hardware is not supported to check CLKOUT pin for system clock, we configured SCK clock for calculating system clock.

  • In below code used as provided by ST, but we facing a problem in free running the code ( debug port fail) while debugging the code in TRACE32.
    For below configuration, code is running some exceptional condition. No system clock generation.
    FMPLL.ESYNCR2.R = 0x00000001;
    FMPLL.ESYNCR1.R = 0xF005002D
    while (FMPLL.SYNSR.B.LOCK != 1) {}; /* Wait for FMPLL to LOCK */
    FMPLL.ESYNCR2.R = 0x00000000;

NOTE: For above configuration the parameters values EPREDIV, ERFD and EMFD is not satisfying for 150Mhz system clock generation if we substitute in enhanced mode formula. Im confused!!!!!

 

  •  In below code used as provided by ST, but we facing a problem in free running the code ( debug port fail) while debugging the code in TRACE32.
    For below configuration, code is running some exceptional condition. No system clock generation.
    FMPLL.ESYNCR2.R = 0x00000000;
    FMPLL.ESYNCR1.R = 0xF005002D;
    while (FMPLL.SYNSR.B.LOCK != 1) {}; /* Wait for FMPLL to LOCK */
    FMPLL.ESYNCR2.R = 0x00000000;

 

  • In below code we referred reference manual of SPC564A80B4. Here we not facing problem debug port fail. The code is free running in debug condition.
    For below configuration, system clock is 72Mhz
    FMPLL.ESYNCR2.R = 0x00000001;
    FMPLL.ESYNCR1.R = 0xF005002D
    while (FMPLL.SYNSR.B.LOCK != 1) {}; /* Wait for FMPLL to LOCK */
    FMPLL.ESYNCR1.R |= 0x70000000;

 

  • In below code we referred reference manual of SPC564A80B4, but we facing a problem in free running the code ( debug port fail) while debugging the code in TRACE32.
    For below configuration, system clock is 150Mhz.
    FMPLL.ESYNCR2.R = 0x00000000;
    FMPLL.ESYNCR1.R = 0xF005002D
    while (FMPLL.SYNSR.B.LOCK != 1) {}; /* Wait for FMPLL to LOCK */
    FMPLL.ESYNCR1.R |= 0x70000000;

 

Please do needful and give us solution resolve this issue, the project is in critical condition. If any documents related to issue please do share to my ID below mentioned.

 

Regards 

Mahesh chamaraja

Office ID : mahesh.chamaraja@kpit.com

Phone No : +917259205624

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