AnsweredAssumed Answered

Which of the several signals from a STM32L4xx timer compare event is connected to the ADC external triggers group?

Question asked by rbv on Jan 16, 2017
Latest reply on Jan 16, 2017 by rbv

I have a data collection system build around an STM32L417RG.  I have configured Timer4 to provide a timebase for triggering the DAC and ADC peripherals.  Because I don't want the DAC output to change during the ADC sampling interval, I have configured the timer in downcounting mode and setup one of the capture/compare registers with a value corresponding to the ADC sample time.  In this way the CC4 event should trigger the ADC sampling and conversion, then the wraparound event should trigger the DAC.

 

However, while I've been able to put the ADC in software-trigger mode (EXTEN = 00) and set ADSTART = 1 inside the Timer4 interrupt handler, my attempts to do this without CPU intervention using a hardware trigger (EXTEN = 01, EXTSEL = 0101) have failed so far.

 

There are quite a number of output signals from the Timer4 peripheral associated with CC4: OC4REF shown on the block diagram, DMA event (enable by CC4DE bit in DIER), Interrupt "CC4I" (enable by CC4IE bit in DIER), "OC4" output signal  (CC4E in CCER) going to pin "TIM4_CH4" (controlled by GPIO alt function select).  Which of these signals is the one connected into the ADC hardware triggers block, where it is named "TIM4_CC4"?

 

The block diagram mentions only that the TRGO signal reaches the ADC, but it seems clear this is EXTSEL=1100 which is distinct from EXTSEL=0101, and don't want to use the TRGO for the ADC since I need it for the DAC.

 

Very similar questions regarding other STM32 families:

 

 

 

Here are the register values from the timer and the ADC

 

-          TIM4->CR1     0x00000015     uint32_t
            UIFREMAP 0     [1 bit]
            CKD      00    [2 bits]
            ARPE     0     [1 bit]
            CMS      00    [2 bits]
            DIR      1     [1 bit]
            OPM      0     [1 bit]
            URS      1     [1 bit]
            UDIS     0     [1 bit]
            CEN      1     [1 bit]
-          TIM4->CR2     0x00000020     uint32_t
            MMS2     0000  [4 bits]
            OIS6     0     [1 bit]
            OIS5     0     [1 bit]
            OIS4     0     [1 bit]
            OIS3N    0     [1 bit]
            OIS3     0     [1 bit]
            OIS2N    0     [1 bit]
            OIS2     0     [1 bit]
            OIS1N    0     [1 bit]
            OIS1     0     [1 bit]
            TI1S     0     [1 bit]
            MMS      010   [3 bits]
            CCDS     0     [1 bit]
            CCUS     0     [1 bit]
            CCPC     0     [1 bit]
+          TIM4->SMCR     0x00000000     uint32_t
+          TIM4->DIER     0x00000011     uint32_t
+          TIM4->SR       0x0000001f     uint32_t
+          TIM4->EGR      0x00000000     uint32_t
+          TIM4->CCMR1    0x00000000     uint32_t
-          TIM4->CCMR2    0x00001000     uint32_t
             OC4CE    0     [1 bit]
            OC4M     0001  [4 bits]
             OC4PE    0     [1 bit]
            OC4FE    0     [1 bit]
            CC4S     00    [2 bits]
             OC3CE    0     [1 bit]
            OC3PE    0     [1 bit]
            OC3FE    0     [1 bit]
            CC3S     00    [2 bits]
-          TIM4->CCER     0x00001000     uint32_t
             CC6P     0     [1 bit]
            CC6E     0     [1 bit]
            CC5P     0     [1 bit]
            CC5E     0     [1 bit]
             CC4NP    0     [1 bit]
            CC4P     0     [1 bit]
            CC4E     1     [1 bit]
             CC3NP    0     [1 bit]
            CC3NE    0     [1 bit]
            CC3P     0     [1 bit]
            CC3E     0     [1 bit]
            CC2NP    0     [1 bit]
            CC2NE    0     [1 bit]
            CC2P     0     [1 bit]
            CC2E     0     [1 bit]
            CC1NP    0     [1 bit]
            CC1NE    0     [1 bit]
            CC1P     0     [1 bit]
            CC1E     0     [1 bit]
+          TIM4->CNT      0x00000557     uint32_t
+          TIM4->PSC      0x00000000     uint32_t
          TIM4->ARR      0x0000059f     uint32_t
+          TIM4->RCR      0x00000000     uint32_t
+          TIM4->CCR1     0x00000000     uint32_t
+          TIM4->CCR2     0x00000000     uint32_t
+          TIM4->CCR3     0x00000000     uint32_t
-          TIM4->CCR4     0x00000064     uint32_t
+          TIM4->BDTR     0x00000000     uint32_t
+          TIM4->DCR      0x00000000     uint32_t
+          TIM4->DMAR     0x00000015     uint32_t
          TIM4->OR1      0x00000000     uint32_t
+          TIM4->CCMR3    0x00000000     uint32_t
+          TIM4->CCR5     0x00000000     uint32_t
+          TIM4->CCR6     0x00000000     uint32_t
          TIM4->OR2      0x00000000     uint32_t
          TIM4->OR3      0x00000000     uint32_t

 

+          ADC1->ISR      0x0000001e     uint32_t
+          ADC1->IER      0x00000014     uint32_t
-          ADC1->CR       0x10000005     uint32_t
             ADCAL     0     [1 bit]
             ADCALDIF  0     [1 bit]
             DEEPPWD   0     [1 bit]
             ADVREGEN  1     [1 bit]
             JADSTP    0     [1 bit]
             ADSTP     0     [1 bit]
             JADSTART  0     [1 bit]
             ADSTART   1     [1 bit]
             ADDIS     0     [1 bit]
             ADEN      1     [1 bit]
-          ADC1->CFGR     0x00000540     uint32_t
             JQDIS     0     [1 bit]
             AWD1CH    00000 [5 bits]
             JAUTO     0     [1 bit]
             JAWD1EN   0     [1 bit]
             AWD1EN    0     [1 bit]
             AWD1SGL   0     [1 bit]
             JQM       0     [1 bit]
             JDISCEN   0     [1 bit]
             DISCNUM   000   [3 bits]
             DISCEN    0     [1 bit]
             AUTDLY    0     [1 bit]
             CONT      0     [1 bit]
             OVRMOD    0     [1 bit]
             EXTEN     01    [2 bits]
             EXTSEL    0101  [4 bits]
             ALIGN     0     [1 bit]
             RES       00    [2 bits]
             DMACFG    0     [1 bit]
             DMAEN     0     [1 bit]
+          ADC1->CFGR2     0x00000000     uint32_t
+          ADC1->SMPR1     0x00600000     uint32_t
+          ADC1->SMPR2     0x00000000     uint32_t
+          ADC1->TR1       0x0fff0000     uint32_t
+          ADC1->TR2       0x00ff0000     uint32_t
+          ADC1->TR3       0x00ff0000     uint32_t
+          ADC1->SQR1      0x000001c0     uint32_t
+          ADC1->SQR2      0x00000000     uint32_t
+          ADC1->SQR3      0x00000000     uint32_t
+          ADC1->SQR4      0x00000000     uint32_t
+          ADC1->DR        0x000007fd     uint32_t
+          ADC1->JSQR      0x00000000     uint32_t
+          ADC1->OFR1      0x00000000     uint32_t
+          ADC1->OFR2      0x00000000     uint32_t
+          ADC1->OFR3      0x00000000     uint32_t
+          ADC1->OFR4      0x00000000     uint32_t
+          ADC1->JDR1      0x00000000     uint32_t
+          ADC1->JDR2      0x00000000     uint32_t
+          ADC1->JDR3      0x00000000     uint32_t
+          ADC1->JDR4      0x00000000     uint32_t
+          ADC1->AWD2CR    0x00000000     uint32_t
+          ADC1->AWD3CR    0x00000000     uint32_t
+          ADC1->DIFSEL    0x00000000     uint32_t
+          ADC1->CALFACT   0x0000003c     uint32_t

Outcomes