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Clear pending interrupts

Question asked by woolston.jared on Aug 15, 2014
Latest reply on Aug 15, 2014 by woolston.jared
I know for a fact that this question has been asked before (I've seen it) but for the life of me I cannot find it, so I appologize.

I am unable to get some of my EXTI interrupts to clear their pending status. I remember reading in the previously mentioned post that the clear is buffered and that a read should force the write to complete. This is also mentioned in this FAQ. The CMSIS library is useless for this as the NVIC_GetPendingIRQ reads from ISPR register and the clear obviously goes to ICPR register. So I tried using NVIC_ClearPendingIRQ() followed by a direct read of NVIC->ICPR, but it still stays set. I know there is no signal on the EXTI line which would be asserting it at the time. 

I configure the interrupt as follows:
GPIO_InitTypeDef GPIO_InitStructure;
 
    /* Enable GPIOA clock */
    HOST_SPI_ACTIVE_CLK_ENABLE();
 
    /* Configure PA2 pin as input floating */
    GPIO_InitStructure.Mode = GPIO_MODE_IT_RISING;
    GPIO_InitStructure.Pull = GPIO_NOPULL;
    GPIO_InitStructure.Pin = HOST_SPI_ACTIVE_PIN;
    GPIO_InitStructure.Speed = GPIO_SPEED_HIGH;
    HAL_GPIO_Init(HOST_SPI_ACTIVE_PORT, &GPIO_InitStructure);
 
    /* Enable and set EXTI Line7 Interrupt to the lowest priority */
    HAL_NVIC_SetPriority(HOST_SPI_ACTIVE_EXTI_IRQn, HOST_SPI_ACTIVE_IRQ_PREEMPT_PRI, HOST_SPI_ACTIVE_IRQ_SUB_PRI);
    HAL_NVIC_EnableIRQ(HOST_SPI_ACTIVE_EXTI_IRQn);

My attempts to clear the interrupt prior to re-enabling it after I had previous disabled it follow:
uint32_t pending = HAL_NVIC_GetPendingIRQ(HOST_SPI_ACTIVE_EXTI_IRQn);
printf("SPI Active interrupt pending? %" PRIu32 "\n\r", pending);
HAL_NVIC_ClearPendingIRQ(HOST_SPI_ACTIVE_EXTI_IRQn);
pending = NVIC->ICPR[0];
pending = HAL_NVIC_GetPendingIRQ(HOST_SPI_ACTIVE_EXTI_IRQn);
printf("SPI Active interrupt post clear pending? %" PRIu32 "\n\r", pending);
HAL_NVIC_EnableIRQ(HOST_SPI_ACTIVE_EXTI_IRQn);

After the enable call the interrupt is immediately fired, even though the GPIO line in question is logic low (confirmed by logic analyzer)

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