For the past month I have been developing a device that has multiple features on an STM32F103ZG, with the intentions of basically replacing the chip and migrating the code with an STM32F427ZI when I was closer to completion.
The devices are mostly pin compatible with very small alteration to the ADC power, but my issue is with SPI.
The device is set as an SPI2 slave on receive only with hardware NSS signal. The associated pins are MOSI (PB15), SCK(PB13) and NSS (PB12). The SCK waveform is pretty consistent with slight random and intermittent delays, but the entire structure is fine and not really any different from another other SPI waveform I’ve seen using a Logic Analyzer.
On the STM32F103 it works great and everything goes as intended. I am using DMA to load incoming SPI data into an array. On the STM32F427 it does not work properly. It constantly misses bits which forces it out of alignment. Once out of alignment it will repeat the behaviour for a while until it either kicks back into alignment from missing another set of bits, or it will kick into another random alignment all together.
The STM32 is running at 3V, and the incoming signal is 5V. I didn’t want to rely on if the respective pins were 5V Tolerant between the chipsets, so I decided to level shift the input with a 4050 non-inverting hex buffer. This setup works perfectly on the STM32F103, but not so on the STM32F427. After thinking about it for a while, I wasn’t confident that the 4050 wasn’t creating an issue for the STM32F427. I decided to use a resistor voltage divider on each pin instead of the 4050 to get the voltage to 3V but the result was the same on the STM32F427. It was constantly getting out of sync. I didn’t test that setup on the STM32F103, but a few years ago I created a device with an identical incoming SPI signal to an STM32F103CB and resistor voltage divider network and it worked then.
In STM32CubeMX, the SPI2 Clock Prescaler is accessible on the STM32F103 but not on the STM32F427. The prescaler that I use on the STM32F103 is 256, resulting in a 140.625 Kbit/s baud rate. I have always wondered why that was put in place for slave devices as the speed of communication is dictated by the speed of the SCK on the Master device, so when I noticed it missing from the STM32F427 it seemed natural for it to be that way. I’m thinking now that it’s as if it was necessary and I didn’t notice the complete purpose for having that as a Slave device.
I’m not sure what I’m missing now. Does anyone have any suggestions?