RM0367 Rev.5, Ch. 6.1.6 Dynamic voltage scaling configuration requires to
Poll VOSF bit of in PWR_CSR. ait until it is reset to 0.
twice. The note at the end of the same chapter says,
During voltage scaling configuration, the system clock is stopped until the regulator is
Now how could (and why should) the processor poll for VOSF if it's effectively stopped?