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RM0367 (STM32L0x3) discrepancies

Question asked by waclawek.jan on Jan 10, 2017
Latest reply on Mar 4, 2018 by waclawek.jan


RM0367 Rev.5, Ch. 6.1.6  Dynamic voltage scaling configuration requires to

Poll VOSF bit of in PWR_CSR. ait until it is reset to 0.

twice. The note at the end of the same chapter says,

During voltage scaling configuration, the system clock is stopped until the regulator is
stabilized (VOSF=0).

Now how could (and why should) the processor poll for VOSF if it's effectively stopped?