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spi frame

Question asked by mulcock.andrew on Jan 6, 2017
Latest reply on Jan 6, 2017 by mulcock.andrew

Looking at the STM32F7 , going to H7 when available.

 

Have some external peripherals that are SPI , but, need 24 bits of data in  a frame.

     i.e. the SPI CS goes active for 24 data bits, then in active at the end, CS must not rise during the transfer.

 

Looking at the SPI controllers, looks like they can handle up to 16 bits !

 

First thought was, lets us a gpio as the CS bit, and send out two frames.

 

Any thoughts on if this is the way, or can I trick the SPI controllers to generate a 24 bit spi stream,

    

Any thoughts on should I load the SPI as two 'words' of 12 bits, or one of 8 and one of 16 ?

   How would the FIFO on the SPI handle that.

 

Need a fairly fast speed here, and minimum CPU time, would like to 'send and forget'.

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