I see strange behavior of L6482H output toward FET gate, I'm expecting that the high side output amplitude will be the Vboot (Vs+Vcp) to allow proper Vgs and low Rdson over the FET but some time the amplitude is Vs instead.
For example if I'm moving the motors from A to B than backward, one direction the driver output can be Vboot while the other direction is Vs.
Vs=48V, Vboot=~60V (stable)
The low Vgs leads to high differential voltage (Vds) that cause to overcurrent event, although the current is low.
To my opinion it's not related to driver timing setting.
Any idea why the high side output amplitude that should be Vboot (Vs+Vcp) sometimes Vs?