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STM32F7 series need separate SDMMC PLL

Question asked by David Harrison on Dec 31, 2016
Latest reply on Jan 1, 2017 by Clive One

Hi all. The standard SDMMC bus speed is 24MHz which, on the STM32F7 series, is derived from the USB PLL48 clock source / 2. If we want to operate the SD card in High Speed mode, which has a maximum bus speed of 50MHz, the SDMMC peripheral needs a clock source of 100MHz.

 

However, the only clock source options available for the SDMMC peripheral are PLL48 or SYSCLK. That means if you want to use SDMMC in high speed mode you are limited to a SYSCLK of 200MHz using the SDMMC CLKDIV set to 2 for a total divider ratio of 4, rather than the maximum 216MHz possible for SYSCLK. Or at 216MHz, the SD card bus would be 54MHZ. I don't if most modern SD cards will accept a clock speed that fast? Does anyone else know?

 

This seems a silly oversight on STM's part. What we need is a completely independent PLL for SDMMC clock so it can be clocked at its maximum speed regardless of the PLL48 or SYSCLK.


And, as an aside, why have STM chosen to call the SD card interface "SDMMC" and not "SDIO" on their latest and most up to date chips? It was called SDIO in the STM32F4 series, and who uses MMC cards these days anyway? It seems a silly and unnecessary name change for this peripheral to me.

 

Will STM PLEASE take note of this and introduce a separate SDMMC PLL in their next generation of pin compatible F7 chips?

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