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Wrong FLASH_ACR->LATENCY bit in stm32f103xe.h?

Question asked by Kietzmann.Peter on Dec 22, 2016
Latest reply on Jan 6, 2017 by Kietzmann.Peter

Section 3.3.3 of the reference manual (RM0008, Rev16) for STM32F10XXX MCUs explains in the register description for FLASH_ACR->LATENCY:

 

Bits 2:0 LATENCY: Latency
These bits represent the ratio of the SYSCLK (system clock) period to the Flash access time.
000 Zero wait state, if 0 < SYSCLK≤ 24 MHz
001 One wait state, if 24 MHz < SYSCLK ≤ 48 MHz
010 Two wait states, if 48 MHz < SYSCLK ≤ 72 MHz

 

If I see it correctly, the CMSIS header stm32f103xe.h defines odd bits for this purpose:

 

#define FLASH_ACR_LATENCY_0                 (0x1U << FLASH_ACR_LATENCY_Pos)    /*!< 0x00000001 */
#define FLASH_ACR_LATENCY_1                 (0x2U << FLASH_ACR_LATENCY_Pos)    /*!< 0x00000002 */
#define FLASH_ACR_LATENCY_2                 (0x4U << FLASH_ACR_LATENCY_Pos)    /*!< 0x00000004 */

 

In previous versions of the header file this wasn't the case, even thought the documentation of these bits appears a bit confusing:

 

  * @file    stm32f10x.h
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    11-March-2011

...

#define  FLASH_ACR_LATENCY                   ((uint8_t)0x03)               /*!< LATENCY[2:0] bits (Latency) */
#define  FLASH_ACR_LATENCY_0                 ((uint8_t)0x00)               /*!< Bit 0 */
#define  FLASH_ACR_LATENCY_1                 ((uint8_t)0x01)               /*!< Bit 0 */
#define  FLASH_ACR_LATENCY_2                 ((uint8_t)0x02)               /*!< Bit 1 */

 

Best regards

Peter

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