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STM32F746 Startup-Problem with DCache - AN4667

Question asked by ada_fan on Dec 16, 2016
Latest reply on Feb 6, 2018 by Július Kovács

Hello,

 

I have problems with a STM32F746 and DCache. Without DCache my software runs perfectly. If I enable the DCache (first invalidate it and the Enable), then I can't start the board.

I have check my source code, the document (Programmer Manual from STM32, the AN4839 [L1-Cache on STM32F7], the errata of Cortex M7 and STM32F746, but I have no idea.

After a power on, the processor runs in a hard fault. The IMPRECISERR in System Control - Bus Fault Status register and the AXIM-Bit in ABFSR (Auxiliary Bus Fault Status register) are set. The AXIM Type is 2.

If I understand this bits right then someone write (due to the IMPRECISERR) on wrong address via the AXIM-Bus. The AXIM-Slaves are the FLASH, SRAM, FMC and QUAD-SPI. I don't use FMC and Quad-SPI. FLASH is read only - therefor I suggest the problem is according to the SRAM. This can match to a problem with the DCache. (Incorrect invalidate?)

 

In the AN4667 (STM32F7 Series system architecture and performance) I found one sentence which I don't understand: Page 43 - last sentence (Chapter 4.2 Tips, last sentence).

"It is not recommended to enable the cache before calling the main function, that is, before the scatter load phase, because a hard fault may occur".

What means this? Why a hard fault does occur? Is this a reason for my problem?

 

Best regards, Michael

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