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STMCubeMX 4.18.0 generates incorrect PLL timing

Question asked by Elwood Downey on Dec 5, 2016
Latest reply on Jul 5, 2017 by Sirma Siang

I am using STMCubeMX 4.18.0 configured for STM32F446ZET. When I set Clock Configuration HCLK to 180 the following lines in main.c cause the processor to hang:

 

  RCC_OscInitStruct.PLL.PLLM = 4;

  RCC_OscInitStruct.PLL.PLLN = 180;

  RCC_OscInitStruct.PLL.PLLQ = 2;

  RCC_OscInitStruct.PLL.PLLR = 2;

 

Changing to the following allows the processor to run correctly at 180 MHz:

 

 

  RCC_OscInitStruct.PLL.PLLM = 16;

  RCC_OscInitStruct.PLL.PLLN = 360;

  RCC_OscInitStruct.PLL.PLLQ = 7;

  RCC_OscInitStruct.PLL.PLLR = 7;

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