I use ST/Raissonance Rlink with RIDE 7 and gcc.
On 16-10-2008 at 22:36, Anonymous wrote:
Did anyone check the DSP lib for STM32? Unless this lib is rather poorly written I'd say that STM32 is not so great performer. Also there is close to none performance gain when code is executed at 72 MHz compared to 48 Mhz. Not worth the extra mA.
On 20-10-2008 at 11:05, Anonymous wrote:
What is the ACR register of the STM32? What STM32 did you use?
I have benched the STM32F103RB (STM32 Primer) and adding 2 wait-state decrease significantly the performance. BTW, there is absolutely nothing in the stm32f103rb datasheet about peripherals interface (registers, ...).
On 20-10-2008 at 16:45, Anonymous wrote:
The ACR is documented in the Flash programming manual. (13259.pdf) According to this, bit 4 in the ACR is the prefetch buffer enable bit.
Obviously turning on the prefetch will speed up sequential accesses and remove some of the hit you take by having wait states.
Hmmm... I have tested again the 1 and 2 wait-states configuration, but with the (1<1. What is this bit exactly? Is it a kind of flash "accelerator" ?
2. It is not documented in the RM0008.pdf (Reference Manual for Low-, medium- and high-density STM32F101xx, STM32F102xx
and STM32F103xx advanced ARM-based 32-bit MCUs).
3. Is-there drawbacks or limitation when using this "hidden" feature?
. With 0 WS, my bench uses 67476 cycles
. With ACR=0x01 (1 WS), my bench uses 97728 cycles.
. With ACR=0x11 (1 WS), my bench uses now 71904 cycles.
I would like to know if I can use this feature even if this is not documented...
On 16-10-2008 at 13:35, Anonymous wrote:
I'm working on a STM32 product (STM32 Primer) and have ported Dhrystone 2.1.
Squonk, If I look to your best score (you said "55260 Dhrystone/s"), that means that you achieve about 31.45 DMips (I divided by 1757, the number of Dhrystones per second obtained on the VAX 11/780, nominally a 1 MIPS machine - http://en.wikipedia.org/wiki/Dhrystone)
But compared to your frequency, which is 72MHz, that gives... only 0.43 DMips /MHz!!!
The product is supposed to be about 1.25DMips/MHz without wait state. I do not know with 2 wait-state, but that's a big difference.
I have tested Dhrystone on my STM32 Primer (or STM32Circle), and I have (with -O3, at 12MHz / 0 Wait state): 0.70 DMips/MHz. This is far from the 1.25 number given on the datasheet.
Can anyone please explain me how to achieve the 1.25 number?
On 20-10-2008 at 17:57, Anonymous wrote:
I think the means to achieve 1,25DMips/MHz is to operate the device at 48MHz with 0 wait states. In this case You achieve the highest DMips/MHz value but not the fastest processor.
Additionally it might be necessary to use a "better" compiler. I was using the GNU tool chain. I think with Green Hills or Keil it will be possible to achieve better results.
With 0 wait-state, I have 0.70 DMips/MHz, which seems coherent (the drop with/without wait state seems reasonable).
On 21-10-2008 at 13:27, Anonymous wrote:
Where did you get this "MISP test"?
Retrieving data ...