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IIS2DH interrupt generation and tech details

Question asked by Marco Pappalardo on Nov 4, 2016
Latest reply on Dec 16, 2016 by Miroslav B

I would like to use IIS2DH accelerometer as main accelerometer in a custom board for my project. For this reason I've bought the STEVAL-MK1168V1 to make some tests. I would like to ask you some questions about this product, since they are not well specified in the datasheet I've downloaded from the product page site.

1) I usually program with Atmel microcontrollers, so I've made the same this time. What I've done is to link both i2c pins, Vdd and Vdd_io to Vcc=3v3, GND and both INT1 and INT2 pins. i2c communication works fine but i can't handle interrupts generated through INT pins.
I set the Int1_cfg register to binary 00111111 (OR combination of all axis events), the I1_A01 bit on ctrl_reg3 to 1 and, after moving the board, I cheked the int1_src register I've seen that IA, ZH, YH, XH bits are set, so what I've expected was an interrupt on INT1 pin, but the corresponding callback on microcontroller doesn't start. The callback seems to start only if I latch him, setting to 1 the LIR_INT1 on ctrl_reg5, just after reading the int1_src register. The port on microcontroller side is configured as input with pull-down and with rising edge detection, the code works for other uses so I am sure there are no errors on my code. What I ask you is:
- Why I have this behaviour? It is correct or I have to set differently the microcontroller port?
- Can you tell me more about the interrupt generated on INT pins? Which is the waveform used, is it a spike? Which is the duration of the signal?

2) Reading the datasheet I have not understood well which is the meaning of int1_cfg and int1_src registers. If I use the same setting as written before for int1_cfg I have a strange behaviour on int1_src register: it gives me always the value 6A even when I have only negative value read from the output registers. Now, can you tell me more about the AOI-6D setting related to the difference in ZHIE/ZLIE and ZUPE/ZDOWNE? Cause it's not clearly explained on datasheet. I think that the couple ZUPE/ZDOWNE is related to 6-direction movement/position recognition (as expected by the name, I think that if I set the ZUPE the corresponding ZH interrupt will be generated if I move to positive direction in Z axis), but I don't know how to interpret the other couple ZHIE/ZLIE, since what I wrote above (ZH set when reading negative acceleration value on Z axis). 
Perhaps it is related to the OUT_Z_H and OUT_Z_L registers, so ZH would be fired if the OUT_Z_H register is filled? Or to what the "interrupt generation on Z high event" is related?
Moreover which is the meaning of INT1_THS register? Is it used to generate interrupt when a value on every axis enabled in the int1_cfg register overtake the threshold value set, or it is used also to determine the 6-D position/movement recognition?

3) In the datasheet it is written that both INTx_cfg registers are loaded on boot and a write operation is possible only after system boot. What does it mean? Maybe should I set up both this registers correctly is writing on them before any other operation so do I need a sort of external mechanism to reboot the accelerometer every time I need to change the setting of these registers?

4) Can you explain me better what does it mean "reboot memory content" function enabled by setting the BOOT bit on ctrl_reg5?

5) Can you tell me more about the high-pass filter mode configuration HPM[1:0] bits? Which are the differences between them and how I have to interpret the REFERENCE/DATA CAPTURE register in relation to them?

Thank you very much.