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Entering Halt mode with the WWDG enabled causes reset

Question asked by loveland.harry on Jul 15, 2011
Latest reply on Jul 18, 2011 by loveland.harry
I've checked the Option Bytes and the OPT3 byte is zero so the WDG_HALT bit is 0 which according to the data sheet means that the MCU should enter Halt Mode when calling halt() instead of generating a reset.  Following the reset the RST_SR register is set to RST_SR_WWDGF indicating a WWDG reset.  I'm wondering if there is some other condition causing the reset or is the description in the data sheet incorrect?

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