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ADC Accuracy varies with sample clocks

Question asked by Chris D on Nov 28, 2016
Latest reply on May 25, 2017 by wolff.roger
I am having difficulty getting an equivalent ADC accuracy to my old 8 bit uC with 10 bit ADCs. I am looking to see if anyone can explain why changing the ADC clock cycles affects the ADC accuracy. I would expect longer sampling time would average out any noise. Ultimately I need better accuracy. Would I have better luck going to either STM32F1 with less peripherals, or investigate a different uC altogether? Or is this typical for high speed microcontrollers?

I have 4 different ADC inputs with a constant DC input applied from op amps. ADC scan group was sampled at 76 us. ADC DC voltages where measured with a high res DVM (calibrated) very close to the pads. Vref = 3.2924 which I am using to calculate the converted voltage. I cannot measure any noise on DVM or scope. I did gain some ADC noise improvements by adding some VCC and GND wires close to the pins, but did nothing for accuracy and doesn't explain the strange ADC sample clocks.

Example 1: ADC123_IN0
This has op amp directly feeding uP ADC. Reference voltage of 2.4927 V.

Example 2: ADC123_IN1
This input has a op amp followed by a voltage divider with equivalent impedance of 1.3k ohms. STM datasheet calculations show all sample cycles shown are ok. (ADC clock = 12.5 Mhz)

Example 3: ADC123_IN2
Same as above, but different op amp feeding different ADC input.

Example 4: ADC123_IN3
Same as above, but different op amp feeding different ADC input.

I do have a limitation that I'm using a 2 layer board. Bottom side is poured ground around traces. I realize that is difficult to get great ADC results, but that should only affect noise, but does not really explain the accuracy changing with ADC sample time. I did already add a few jumpers which appeared to lower noise but not accuracy.