Hello great STM forum,
in the last 6 months I was developing and manufacturing about 30 units with STM32F427 in LPQF 144 package.
In the meantime I realized the same behaviour on 3 different boards on different production batches and with different STM production codes on the STM chips:
The internal reset pulse generator is not working and therefore no one of the internal reset causes (watchdog, software reset, etc.) will take place (see RM0090, chapter 6.1.2, figure 4).
An external reset on the NRST pin to GND works like it should work, the NRST line normally sits perfect on VDD due to the internal pullup resistor.
The µC was working totally fine, it was just the interal reset which was not working.
I just realized this that when flashing with KEIL IDE and (original) STM STLink the IDE told me that it could not reset the chip.
Changing the KEIL IDE to reset the chip with the "HW reset" was able to flash the chip perfectly.
But any watchdog activities and other internal resets software generated would not take place on the defective boards/µC.
As I could see from the STM documentation the NRST pin is capable of sinking 5mA via its internal (MOS-)FET transistor (see en.DM00071990 table 15).
So question number 1:
Will it break the MOSFET if NRST pin is externally connected to VDD if an internal reset (its just limited 20µs) will get generated? I do not want to test this on purpose before asking - the STM32F427 is quite expensive - so if anybody has some experience with this it would be quite helpful for me. Otherwise I will do some tests in the near future.
"clive1" mentioned in "STM32F4 does not self-reset on power up; BOOT0 is tied to GND" that "Driving NRST by an external push-pull driver will break the device's reset mechanism."
Does "break" mean the hardware (STM32) will get defective or just the µC will not reset like it should do?
I´m not sure and I did not have a detailed look on the STLink schematics, but maybe STLink is driving the NRST pin with a push pull stage instead of a open drain circuitry and therefore is able to damage the µC.
(but i do not think so - this would probably cause a nightmare for STM?!)
Question number 2:
Because there is nearly no chance that something could lead to the situation that is described before (connecting NRST to a VDD level externally) on my boards, I´m asking myself if it is possible that my externally mounted 100nF MLCC capacitor from NRST to GND (like suggested by STM as "recommended NRST pin protection) could lead to a broken internal reset transistor in the µC because the instantaneous current to discharge a fully VDD loaded capacitor is way above 5mA!
This situation is just for a short period, but anyway - maybe it could kill the internal FET because it is like a short time short circuit from GND to VDD.
And because I found a lot of issues here were the NRST is not working properly I could imagine there is an issue with broken internal reset transistors which are permanently closed, permanently open or half open/close which will lead to strange situations.
Could it be that this internal reset transistor is a very sensitive one?
On all working boards an internally generated reset (software reset, watchdog, etc.) generates a 20µs low level pulse on the NRST pin which will increase exponentially up to VDD again (for sure depending on the externally capacitor and the internal pull up resistior.)
I was searching all STM errata sheets and could not find anything.
By the way: In all of the 3 mentioned situations - changing the STM32F427 on the board was curing the situation, so there was no problem with the board itself. Also PC13, PC14 & PC15 are not connected on the board.
I would appreciate to find some fellows or get any valuable information...