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Bit RFWRA in register MACDBGR is never set!!!!!!

Question asked by kashuba.dmitry on Nov 15, 2016
Latest reply on Nov 15, 2016 by kashuba.dmitry
Hi!
I have LAN8720, STM32F4DISCOVERY, CP2102
I connected PC-LAN8720, LAN8720-STM32F4DISC, STM32F4DISC-CP2102, CP2102-PC.
I wrote such program for STM32F407:
//Ethernet
/*******************************************************************/
//pc6-usart6_tx,pc7-usart6_rx
//pb13-tx1, pb11-txen, pb12-tx0, pc4-rx0, pc5-rx1, pa1-refclk, pa7-crs, pa2-mdio,pc1-mdc
#include "stm32f4xx.h"
uint32_t i, temp;
int main()
{
//config clock
RCC->CR=(RCC_CR_HSEON|RCC_CR_PLLON|RCC_CR_CSSON);//extern quartz,pll,(|
RCC->PLLCFGR=0x00005408;//n=210, m=10, hs=8 MHz
//RCC->CFGR=(RCC_CFGR_SW_PLL|RCC_CFGR_SWS_PLL|RCC_CFGR_MCO1);//mco1,system clock from PLL
RCC->CFGR=0x0760940A;
while (!(RCC->CR&0x02000000));

//enable gpio, usart6, mac
RCC->AHB1ENR=(RCC_AHB1ENR_ETHMACRXEN|RCC_AHB1ENR_ETHMACTXEN|RCC_AHB1ENR_ETHMACEN|RCC_AHB1ENR_GPIOAEN|RCC_AHB1ENR_GPIOBEN|RCC_AHB1ENR_GPIOCEN|RCC_AHB1ENR_GPIODEN);//vkl takt port a-d,mac
RCC->APB2ENR=(RCC_APB2ENR_SYSCFGEN|RCC_APB2ENR_USART6EN);

//config type GPIO
GPIOA->MODER|=(GPIO_MODER_MODER1_1|GPIO_MODER_MODER2_1|GPIO_MODER_MODER7_1|GPIO_MODER_MODER8_1);
GPIOB->MODER|=(GPIO_MODER_MODER12_1|GPIO_MODER_MODER13_1|GPIO_MODER_MODER15_1);
GPIOC->MODER=(GPIO_MODER_MODER1_1|GPIO_MODER_MODER4_1|GPIO_MODER_MODER5_1|GPIO_MODER_MODER6_1|GPIO_MODER_MODER7_1);
GPIOD->MODER=0x55000000;//VIVODI PD15-PD12 - VIHOD

//config altern func     
     GPIOA->AFR[0]=0xB0000BB0;//mac
     GPIOB->AFR[1]=0xB0BB0000;//mac
     GPIOC->AFR[0]=0x88BB00B0;//PC6,PC7-USART6,mac

//conf usart6     
     //USART6->BRR=0x0341;//0x0341,8 MHz to 9600 bps
     USART6->BRR=0x8b;//8 MHz to 115200 bps
     USART6->CR1|=(USART_CR1_OVER8|USART_CR1_RE|USART_CR1_TE|USART_CR1_UE);//over8=1,UE,TE,RE

//set rmii interface
SYSCFG->PMC=SYSCFG_PMC_MII_RMII_SEL;

//config LAN8720
ETH->MACMIIDR=0x00001000;//auto-negotiation
ETH->MACMIIAR=0x00000803;//adr=1, reg=0,write     
while (ETH->MACMIIAR==0x00000803);
for (i=0;i<10;i++);

while (1)
{
ETH->MACMIIAR=0x00000841;//adr=1, reg=1,read
while (ETH->MACMIIAR==0x00000841);

while (!(ETH->MACMIIDR&0x0004))//link is up?
{//no
     ETH->MACMIIAR=0x00000841;//adr=1, reg=1,read
  while (ETH->MACMIIAR==0x00000841);
     GPIOD->ODR=0x00004000;
}

GPIOD->ODR=0x00001000;//yes
for (i=0;i<10000;i++);
GPIOD->ODR=0x00000000;//yes

//out reg 1
temp=ETH->MACMIIDR;
USART6->DR=temp;
while (!(USART6->SR&USART_SR_TXE));

temp=temp>>8;
USART6->DR=temp;
while (!(USART6->SR&USART_SR_TXE));

ETH->MACMIIAR=0x00000fc1;//adr=1, reg=31,read
while (ETH->MACMIIAR==0x00000fc1);

//out reg31
temp=ETH->MACMIIDR;
USART6->DR=temp;
while (!(USART6->SR&USART_SR_TXE));

temp=temp>>8;
USART6->DR=temp;
while (!(USART6->SR&USART_SR_TXE));

//config MAC
ETH->MACCR=0x02008080;//crsc strip, pad/crc strip
switch(ETH->MACMIIDR)
{
     case 0x1044:ETH->MACCR|=0x00008000;//10,h
     break;
     case 0x1054:ETH->MACCR|=0x00008800;//10,f
     break;     
  case 0x1048:ETH->MACCR|=0x0000c000;//100,h
     break;
  case 0x1058:ETH->MACCR|=0x0000c800;//100,f
     break;
     default: GPIOD->ODR=0x00004000;
     while (1);
     break;
}
ETH->MACCR|=0x00000004;//re
GPIOD->ODR=0x00001000;

//out MACCR
temp=ETH->MACCR;
USART6->DR=temp;
while (!(USART6->SR&USART_SR_TXE));

temp=temp>>8;
USART6->DR=temp;
while (!(USART6->SR&USART_SR_TXE));

temp=temp>>8;
USART6->DR=temp;
while (!(USART6->SR&USART_SR_TXE));

temp=temp>>8;
USART6->DR=temp;
while (!(USART6->SR&USART_SR_TXE));

while (!(ETH->MACDBGR&0x00000010))
{
     GPIOD->ODR=0x00008000;//yes
}
GPIOD->ODR=0x00001000;//yes
while (1);

//out MACDBGR
temp=ETH->MACDBGR;
USART6->DR=temp;
while (!(USART6->SR&USART_SR_TXE));


temp=temp>>8;
USART6->DR=temp;
while (!(USART6->SR&USART_SR_TXE));


temp=temp>>8;
USART6->DR=temp;
while (!(USART6->SR&USART_SR_TXE));


temp=temp>>8;
USART6->DR=temp;
while (!(USART6->SR&USART_SR_TXE));
}
}

There are right impulses on pins rx0, rx1, refclk, crs on LAN8720.
In docklight I saw 2d 78 58 10 84 C8 00 02. (Link is up in LAN8720, speed and mode of ethernet are defined).
Why is bit RFWRA in register MACDBGR not set? What is wrong?
Thank You!

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