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Flash/RAM memory interfaces on STM32F7 series for fast code execution

Question asked by obid.matic on Nov 13, 2016
Hi.

I started to read about Cortex M7 features and how they are implemented into STM32F7 series. I am not sure how to use its different flash/RAM interfaces to gain maximum performance in code execution.

There are several options:

1. executing code through ITCM bus from flash with ART accelerator enabled (0 wait state access)
2. executing code through ITCM bus from ITCM RAM (0 wait state, smaller size)
3. executing code through AXI/AHB bridge from flash with ICache enabled (0 wait state, not sure about that)
4. executing code through AXI/AHB bridge from flash with ICache disabled (slow)

So, my question is, which option is the best? Isn't it the first option which brings 0 wait states on the entire flash memory? Why would anyone use the ITCM RAM, if it is so much smaller in size and has the same latency? Or is there any other reason, not known to me?

Also, what would be benefit of using ICache for code execution from flash through AXI, if the latency is the same as with ART accelerator?

Thanks for sharing your knowledge!

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