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STM32F103RD GPIOC pin 2 default state errata

Question asked by gman on Nov 4, 2016
Latest reply on Nov 6, 2016 by waclawek.jan
While debugging an issue I discovered that on the STM32F103RD/VD silicon, GPIOC pin 2 defaults to SET/1 in the ODR.  All other GPIO ports default to RESET/0.  While it is always good practice to explicitly set the ODR to a default state, in our case we were simply changing GPIOC_2 to a push-pull output and got quite a surprise when the connected circuit went active.

I didn't see this listed in the ST errata document for the STM32 high-density line (DocID14732 Rev 14 / ES0340).  Thought this might help others experiencing unexpected behavior on GPIOC.