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How to realize synchronization offset between DAC and ADC sampling time? Please recommend solution.

Question asked by moshkin.georgy on Nov 2, 2016
Latest reply on Nov 3, 2016 by Chris T
My task is to control and acquire information from distance measurement sensor. Sensor is microwave distance measurement sensor based on FSK modulation.

I am using STM32F407 and HAL libraries. I am familiar with DMA operations and half transfer complete.

STM32 DAC provides 40kHz meander signal to sensor Vtune pin (VCO frequency tuning). Sensor provides single output connected to STM32 ADC working at 40kHz.

DAC one sample time is 
T = 1000 / 40000 = 0.025 ms

ADC and DAC sampling frequency is equal, although ADC sampling time must be much shorter than 0.025ms. Actually it must be something between 0.005 to 0.010ms, right before DAC output meander changes it's voltage. It is required to get correct data from the sensor, because it's output need some time to stabilize after new meander voltage is applied.

Here is an example of timings i want to achieve:
1111s 0000s 1111s 0000s 1111s 0000s

each symbol represents 0.005 ms in time
1 - DAC outputs 3.3v for 0.005 ms
0 - DAC outputs 0v for 0.005 ms
s - ADC acquires one sample for 0.005ms, while DAC continues to work for 0.005ms

Each block  "1111s" is 0.005 x 5 = 0.025 (40kHz sampling frequency)

I do not know how to achieve such offset, so i thought of running ADC at 5x speed of DAC:
ADC frequency: 5 x 40 kHz = 200 kHz
and using only each 5th sample from ADC.
For example, 10 samples ADC DMA buffer, interrupt on half complete takes sample N5 or sample N10 and adds it to 512 samples buffer.
I would prefer to do it in more optimal way, reducing interrupt overhead.

I am using DAC instead of GPIO because external sensor is capable not only of FSK meander modulation, but also linear FMCW modulation, so triangle signals could be applied too (through DAC output to sensors Vtune input).

Thank for your attention, I would be happy to see any comments and suggestions.