I have a general question regarding the sampling time when triggering ADC in DMA mode by using a timer event update.
A little background on my problem:
Sampling 1024 data points from the input signal using ADC+DMA. However, even after using maximum possible clock pre-scalers ADC_CLOCKPRESCALER_PCLK_DIV8 and ADC_SAMPLETIME_480CYCLES for the ADC, the sampling time is high and I cannot see enough periods from my input signal. I cannot increase the buffer size due to memory and processing time restrictions.
I tried to see if using a timer as a trigger for the ADC can solve the issue and can help to reduce the sampling time. But as I have observed, the timer triggers conversion of the whole buffer, not the samples of the buffer. Thus, the sampling frequency still is determined by the main clock and the pre-scaler values.
Any suggestion on how to get around this problem would be appreciated.