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ADC+DMA+TIM: Sampling time

Question asked by RE.KH on Nov 1, 2016
Latest reply on Nov 1, 2016 by Clive One

Hi everyone, 
I have a general question regarding the sampling time when triggering ADC in DMA mode by using a timer event update.

Let’s say I have a DMA buffer with size N. Is it possible to take one ADC sample per each timer trigger and fill in this buffer?  Is there any way that I only get a DMA buffer complete interrupt after acquisition of these N samples?

A little background on my problem:

Sampling 1024 data points from the input signal using ADC+DMA. However, even after using maximum possible clock pre-scalers ADC_CLOCKPRESCALER_PCLK_DIV8 and ADC_SAMPLETIME_480CYCLES for the ADC, the sampling time is high and I cannot see enough periods from my input signal. I cannot increase the buffer size due to memory and processing time restrictions.
I tried to see if using a timer as a trigger for the ADC can solve the issue and can help to reduce the sampling time. But as I have observed, the timer triggers conversion of the whole buffer, not the samples of the buffer. Thus, the sampling frequency still is determined by the main clock and the pre-scaler values.

Any suggestion on how to get around this problem would be appreciated. 

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