We are using I2C on a STM32F303 in master mode. We have computed the configuration of TIMINGR register using AN4235 (and CodeMX gives same results). We don't use clock stretching.
We are facing an unexpected issue :
- The clock frequency measured on SCL is not the expected one. For 400kHz targeted, we measure roughly 382kHz.
- Moreover, we observe frequencies that differs significantly on different boards.
As a master, we would expect to measure on SCL a fixed frequency. After a lot of investigation, it seems that the effective load capacitance of the bus and its impact on the SCL rise time seems also to impact SCL frequency. In our application, the SCL rise time is not constant as the number of slaves can vary.
Is it possible that the SCL rise time is, by any mean, measured by the I2C peripheral and that the SCL frequency vary according to the measured rise time?
On our opinion, the bus capacitance associated to pullup value should affect the SCL waveform, eventuelly leading to malfunction of rise time is two long but the overall frequency should not change. The I2C block diagram of the reference manual does not show any kind of rise time feeback like a comparator of else. So what ?
Does the I2C peripheral implement a kind of rise time measurement of SCL ?
Can somebody has experience relative to this issue ?
Is there a document with a more detailed explanation on how works the I2C peripheral of the F303 devices ?
And finally the important question : assuming that rise time is highly variable in our application, is there a way to configure I2C peripheral to obtain a precise and fixed SCL frequency ?
Thanks for your help, Regards,