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STM32L051 PLL limit with HSI

Question asked by albert.david.004 on Oct 11, 2016
Latest reply on Oct 11, 2016 by albert.david.004
Using an STM32L051, I am unable to generate a 32MHz system clock from from the PLL using the HSI as the clock source.  I can generate up to 24MHz without trouble, but any attempt to generate higher frequencies results in the system locking up.

This code fails:
    // Select internal 16MHz RC oscillator divided by 4 as clock source
    RCC->CR |= RCC_CR_HSION | RCC_CR_HSIDIVEN;
    // Wait for HSI ready
    while (!(RCC->CR & RCC_CR_HSIRDY));
    // Enable PLL with HSI as source
    RCC->CFGR &= ~RCC_CFGR_PLLSRC_HSE; // set PLL source to HSI
    RCC->CFGR |= RCC_CFGR_PLLMUL24 | RCC_CFGR_PLLDIV3;
    RCC->CR   |= RCC_CR_PLLON;
    // Wait for PLL ready
    while (!(RCC->CR & RCC_CR_PLLRDY));
    // Change system clock to PLL
    RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_SW) | RCC_CFGR_SW_PLL;
    // Update SystemCoreClock to reflect new speed
    SystemCoreClockUpdate();

If you change PLLDIV3 to PLLDIV4, it works, but at 24MHz.

I have tried a wide range of multipliers and divisors, but the limit always seems to be 24MHz.  Is this a known issue?  If so, it is not in the errata.

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