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STM32F7 Async memories with continuous clock FMC_CLK

Question asked by pr242 on Aug 27, 2016

Since ST have consistently failed to fix the synchronous memory read bug, I am thinking about using async access to an FPGA, with continuous clock FMC_CLK.

The ST datasheets give no timing info at all in this regard

The async control signals will follow HCLK or FMC_CLK, but is there any additional data?
Also is the FMC_CLK **always** enabled (i.e. can I clock the FPGA PLL from it) The datasheets are unclear about this,