Note that the maximal duration of filtered pulses depends on two parameters:
· The configuration of the filtering stage respective to a certain timer input. For example, the ETR input filtering stage is configured through the ETF[3:0] control bit-field within the TIMx_SMCR register. The configuration of an input filtering stage implies the selection of a sampling clock source, the setting of the sampling clock frequency and the setting of the minimal time duration of a valid pulse in units of clock cycles of the already configured sampling clock.
You can check the "1.4.1 Filtering stage" part of application note “General porpose Timers Cookbook” AN4776.
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