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STM32F7 SPI pulsed mode problem: how to leave NSS low

Question asked by ramakers.andre on Aug 19, 2016
Latest reply on Nov 4, 2016 by ramakers.andre
Hi all,

I need to interface with a common IC which needs to have the NSS low during the complete message of 32 clocks. I have all working, DMA is triggered by a timer and fills the SPI data register with the complete message. However I don't succeed in having the NSS stay low during the 32 clocks. NSS goes high after 8 or 16 clocks (depending on datasize):
Does anyone have an idea how to keep NSS low during all the 32 clocks? I already tried many things and hoped that the "Sequence handling" handled this... Software handling of NSS is NOT a solution in my case.