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STM32F103VBT6 debugging problem

Question asked by Lukasz Przenioslo on Aug 3, 2016
Latest reply on Aug 3, 2016 by Clive One
Hello there,
Recently I developed a PCB board containing the STM32F103VBT6 MCU. Recently, I was using STM32F4 devices without any problems. For this device however, I am unable to debug my target using Segger's J-Link. The device itself is seen correctly by J-Link commander:

SEGGER J-Link Commander V4.96 ('?' for help)
Compiled Dec 22 2014 09:51:58
DLL version V4.96, compiled Dec 22 2014 09:51:48
Firmware: J-Link ARM V8 compiled Nov 28 2014 13:44:46
Hardware: V8.00
S/N: 268004467
OEM: SEGGER-EDU
Feature(s): FlashBP, GDB
VTarget = 3.274V
Info: TotalIRLen = 9, IRPrint = 0x0011
Info: Found Cortex-M3 r1p1, Little endian.
Info: FPUnit: 6 code (BP) slots and 2 literal slots
Info: TPIU fitted.
Found 2 JTAG devices, Total IRLen = 9:
 #0 Id: 0x3BA00477, IRLen: 04, IRPrint: 0x1, CoreSight JTAG-DP (ARM)
 #1 Id: 0x16410041, IRLen: 05, IRPrint: 0x1, STM32 Boundary Scan
Cortex-M3 identified.
Target interface speed: 100 kHz
J-Link>

I am using eclipse and with arm gnu eclipse plugin for development. When I start to debug the chip, I notice that the erasing and loading part takes really long (a lot longer than when working with F4). Then I am stuck at the first line of the assembly startup code, the mcu is being reset all the time and stops on that line:

/**
 * @brief  This is the code that gets called when the processor first
 *          starts execution following a reset event. Only the absolutely
 *          necessary set is performed, after which the application
 *          supplied main() routine is called.
 * @param  None
 * @retval : None
*/
 
  .section .text.Reset_Handler
  .weak Reset_Handler
  .type Reset_Handler, %function
Reset_Handler:
 
/* Copy the data segment initializers from flash to SRAM */
  movs r1, #0 // <---------------- STUCK HERE
  b LoopCopyDataInit

Jlink console message when resuming:
Program received signal SIGTRAP, Trace/breakpoint trap.
Reset_Handler () at ../Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/startup_stm32f103xb.s:82
82 

I have a lso an evaluation board available with the STM32F103VBT6  chip (this one).
This is the schematic for that board.
For this board I also cant debug, but at least the program counter goes further- it locks at clock configuration (I tried internal, external both dont work).

I find it really hard to figure out whats going on. The problem occurs both for JTAG and SWD protocols. I would appreciate all help.

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