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Delay with Center Aligned PWM triggering an ADC conversion

Question asked by raggini.davide on Aug 1, 2016
Latest reply on Aug 1, 2016 by raggini.davide

Hi,

I’m using a stm32f103 to generate center aligned PWM on which i have synced a dual regular simultaneous injected mode ADC conversion.

I’m using TIM4 as source of the PWM signal and, to launch the ADC acquisition at the center of the signal i’m using the update event checking the direction of the counter (this way i have one acquisition every two update events - i cannot use TIM1 and the related repetition counter).

As you can see from the posted image, the whole ADC acquisition takes 11.5us and starts about 1.4us after the center of the PWM pulse and this is a little trouble. The crucial data to be acquired, are located at the start of the acquisition, first two channels, so 2.2us from the start of the acquisition.

- FET_B_H (red): center aligned pwm signal
- Test_POINT(yellow): set high in the TIM4 ISR routine (along with the ADC SOC) and set back low at the end of the conversion (by the DMA TC1 ISR).

I cannot explain the constant delay of 1.4us between the update event and jump to the ISR code that triggers the ADC conversion. Maybe someone of you can help me to figure this out. Attached you can see the init code for both the ADC and TIM4.

Thank you,
Davide

Screen%20Shot%202016-08-01%20at%2016.14.23.jpg
Screen%20Shot%202016-08-01%20at%2016.15.02.jpg

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