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STM32F7: use of DMA to change CCR1 of timer gives transfer error

Question asked by ramakers.andre on Jul 8, 2016
Latest reply on Jul 8, 2016 by Clive One
Hi all,

I use DMA and linked timers in most of my projects with no problems on STM32F1 and STM32F4. I want to do the same on the STM32F7. 
As a test I want to use a DMA stream to create a changing signal on a PWM output. When I debug the code I see that the DMA has a transfer error but I don't understand why. Here is my initialisation code (which with some minor changes works on STM32F1):

            RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA1, ENABLE);          
            DMA_Cmd(DMA1_Stream7, DISABLE);
            DMA_InitStruct.DMA_Channel = DMA_Channel_3;
            DMA_InitStruct.DMA_PeripheralBaseAddr = (uint32_t)(&(TIM10->CCR1));
            DMA_InitStruct.DMA_Memory0BaseAddr = (uint32_t)&sintab_wa;
            DMA_InitStruct.DMA_DIR = DMA_DIR_MemoryToPeripheral;
            DMA_InitStruct.DMA_BufferSize = (uint32_t)nsamp_;
            DMA_InitStruct.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
            DMA_InitStruct.DMA_MemoryInc = DMA_MemoryInc_Enable;
            DMA_InitStruct.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
            DMA_InitStruct.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
            DMA_InitStruct.DMA_Mode = DMA_Mode_Circular;
            DMA_InitStruct.DMA_Priority = DMA_Priority_High;
            DMA_InitStruct.DMA_FIFOMode = DMA_FIFOMode_Disable;
            DMA_InitStruct.DMA_FIFOThreshold = DMA_FIFOThreshold_1QuarterFull;
            DMA_InitStruct.DMA_MemoryBurst = DMA_MemoryBurst_Single;
            DMA_InitStruct.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
            /* Wait for  DMA_GetCmdStatus() */            
            while(DMA_GetCmdStatus(DMA1_Stream7) != DISABLE)
            /* Flush cashes to memory and wait for flush to complete */
            DMA_Init(DMA1_Stream7, &DMA_InitStruct);  
            /* Enable DMA1 channel3 */
            DMA_Cmd(DMA1_Stream7, ENABLE);

I have both instruction and data cache enabled, is that what's blocking? Can anyone give me some clue why I get the bus error?