AnsweredAssumed Answered

Losing timer compare interrupts

Question asked by SeK on Jul 5, 2016
Latest reply on Jul 5, 2016 by SeK
Hi,

I try to setup two compare channels on TIM5 of a STM32F446 device to generate two independent time triggers. Both triggers have a frequency of approximately 8kHz but differ by a few timer ticks. Hence it is inevitable that both interrupts will coincide after some periods or one interrupt will trigger when the other is serviced in a ISR.


Initially this seems to be an easy task but does not work. When both captures fall together one of the CC interrupts can get lost. It cost me several hours to figure out that this apparently happens when one interrupt is serviced in the ISR and the other raises at the wrong moment. My sample code is like that:

void sek::foc::TIM5_Handler()
{  
  if( TIM5->SR & TIM_SR_CC3IF )
  {
    TIM5->SR &= ~TIM_SR_CC3IF;
     
    if( IRStatus & BIT0 )
    {
      IRStatus &= ~BIT0;
       
      //...do some work here
      TIM5->CCR3 = TIM5->CNT + Ticks3Dist;                                     
    }
    else
    {
      IRStatus |= BIT0;
       
      //...do some work here
      TIM5->CCR3 += Ticks3On;
    }   
  }
     
  if( TIM5->SR & TIM_SR_CC4IF )
  {
    TIM5->SR &= ~TIM_SR_CC4IF;
     
    //...do some work here
    TIM5->CCR4 += TimerEventInterval;
  }
}

As you can see I use CC3 and CC4. CC4 has a fixed interval, CC3 periode toggles with every interrupt. CC4 is the compare that gets lost in most cases. As I add a fixed interval to the compare value it stops triggering when the counter value of the timer is greater then CCR4.

Any idea?

Regards

Outcomes