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SPI slave TX FIFO clearing....

Question asked by wolff.roger on Jun 30, 2016
Latest reply on Jul 1, 2016 by wolff.roger
I have an SPI slave. The master may request data at a faster pace than I can handle in software, so I've set up DMA. I've prepared a buffer etc. 
Now after one transfer, I get an interrupt of the DMA having finished (i.e. master asked for more data than I prepared. In that case, the data sent is "don't care": Don't do that then....) But then the CS goes inactive, and later on the master wants a new pack of data. I need to start the transmission at the beginning again. So on the CS edge interrupts I can reset the DMA module, but the SPI module seems to have a bunch of bytes (3 in the current logic analyser trace) still in the TX fifo.

Do I really need to reset the whole SPI module and reinitialize everything? Or can I clear the TX buffer in some way?

Hmm. Workaround I might try: switch to master mode with a very fast clock. (disable the MOSI pin first). 
P.S. I'm working with STM32F030.