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[Possible hardware bug] Full duplex SPI incorrectly reads last bit of each incoming byte

Question asked by pierre on Jun 5, 2016
Latest reply on Sep 5, 2016 by waclawek.jan

I need two STM32 to communicate with each other and unfortunately I only have a SPI bus available. Hence, I decided to set up a test between two ST boards (one STM32F429 Disco and one STM32F4 Discovery). The 429 is the master and the 407 is the slave.

After many hours of debugging, here is my current situation:
 - I can transmit data from the master to the slave using DMA and it is correcty received by the slave (also using DMA)
 - at the same time, the master indeed receives data from the slave but it is not correct

And it's pretty weird. Usually, my bytes have their last bit flipped. For instance, 0xFF will be come 0xFE and 0x52 will be come 0x53. However, depending on the sequence of bytes, sometimes one byte will be ok (but only for this sequence, and no matter how many times you send this exact sequence).

Has anybody ever faced something like this? I came accross a similar issue on this forum but it affected the whole bus, in my case it's only the MISO pin.

Speaking of which, in order to make the MOSI pin work, I had to set the GPIO speed for SPI CLK and SPI MOSI as low. When their speeds were high,  the slave would receive incorrect data. I figured setting the GPIO speed low would act as a low pass filter and reduce oscillations caused by switching GPIO pin. It sounds a bit extreme, but it worked (well, maybe for an other reason, though, I don't know), but it doesn't work for the MISO pin, no matter which configuration of GPIO speeds I choose.

I hit rock bottom and at that point alternative ideas would be very much welcome. Thanks for your help and experience sharing.