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SPI STM32F091 Sending an Data Array

Question asked by messiaen.sander on May 30, 2016
Latest reply on May 30, 2016 by Clive One
Hello everyone,

I have some serious problems i want to send an array of data with SPI but that doesn't work i used the code from the snippet but i changed it a little bit but it doesn't work also in the code below you can see the code that i use , can someone help me please?

#include "stm32f091xc.h"
#include    <stdio.h>
 
uint8_t SPI1_DATA[] = {0x00,0x00,0x00,0x00,0xE1,0xFF,0x10,0xFF,0xE1,0xFF,0x10,0x00,0xE1,0x00,0xFF,0x00,0xE1,0x00,0x00,0xFF,0xE1,0xFF,0xFF,0x00};
 
void Configure_GPIO_SPI1(void);
void Configure_SPI1(void);
int main(void)
{
  Configure_GPIO_SPI1();
  Configure_SPI1();
  while (1)
  {
    if((SPI1->SR & SPI_SR_TXE) == SPI_SR_TXE) /* Test Tx empty */
  {
    SPI1->DR |= *SPI1_DATA; /* Will inititiate 8-bit transmission if TXE */
  }
  }
}
__INLINE void Configure_GPIO_SPI1(void)
{
  /* Enable the peripheral clock of GPIOA */
  RCC->AHBENR |= RCC_AHBENR_GPIOAEN;
     
  /* (1) Select AF mode (10) on PA4, PA5, PA6, PA7 */
  /* (2) AF0 for SPI1 signals */
  GPIOA->MODER = (GPIOA->MODER
                  & ~(GPIO_MODER_MODER4 | GPIO_MODER_MODER5 | \
                      GPIO_MODER_MODER6 | GPIO_MODER_MODER7))\
                  | (GPIO_MODER_MODER4_1 | GPIO_MODER_MODER5_1 |\
                     GPIO_MODER_MODER6_1 | GPIO_MODER_MODER7_1); /* (1) */
  GPIOA->AFR[0] = (GPIOA->AFR[0] & \
                   ~(GPIO_AFRL_AFRL4 | GPIO_AFRL_AFRL5 |\
                     GPIO_AFRL_AFRL6 | GPIO_AFRL_AFRL7)); /* (2) */
}
__INLINE void Configure_SPI1(void)
{
  /* Enable the peripheral clock SPI1 */
  RCC->APB2ENR |= RCC_APB2ENR_SPI1EN;
 
  /* Configure SPI1 in master */
  /* (1) Master selection, BR: Fpclk/256 (due to C27 on the board, SPI_CLK is set to the minimum)
         CPOL and CPHA at zero (rising first edge) */
  /* (2) Slave select output enabled, RXNE IT, 8-bit Rx fifo */
  /* (3) Enable SPI1 */
  SPI1->CR1 = SPI_CR1_MSTR | SPI_CR1_BR; /* (1) */
  SPI1->CR2 = SPI_CR2_SSOE | SPI_CR2_RXNEIE | SPI_CR2_FRXTH | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0; /* (2) */
  SPI1->CR1 |= SPI_CR1_SPE; /* (3) */
}
void NMI_Handler(void)
{
}
void HardFault_Handler(void)
{
  while (1)
  {
  }
}
void SVC_Handler(void)
{
}
void SysTick_Handler(void)
{
}
 
// Basis klokinstellingen doen
void SystemClock_Config(void)
{
    RCC->CR |= RCC_CR_HSITRIM_4;                                                        // HSITRIM op 16 zetten, dit is standaard (ook na reset).
    RCC->CR  |= RCC_CR_HSION;                                                               // Internal high speed oscillator enable (8MHz)
    while((RCC->CR & RCC_CR_HSIRDY) == 0);                                  // Wacht tot HSI zeker ingeschakeld is
     
    RCC->CFGR &= ~RCC_CFGR_SW;                                                          // System clock op HSI zetten (SWS is status geupdatet door hardware)  
    while((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI);  // Wachten to effectief HSI in actie is getreden
     
    RCC->CR &= ~RCC_CR_PLLON;                                                               // Eerst PLL uitschakelen
    while((RCC->CR & RCC_CR_PLLRDY) != 0);                                  // Wacht tot PLL zeker uitgeschakeld is
     
    RCC->CFGR |= RCC_CFGR_PLLSRC_HSI_PREDIV;                                // 01: HSI/PREDIV selected as PLL input clock
    RCC->CFGR2 |= RCC_CFGR2_PREDIV_DIV2;                                        // prediv = /2      => 4MHz
    RCC->CFGR |= RCC_CFGR_PLLMUL12;                                                 // PLL multiplied by 12 => 48MHz
     
    FLASH->ACR |= FLASH_ACR_LATENCY;                                                //  meer dan 24 MHz, dus latency op 1 (p 67)
     
    RCC->CR |= RCC_CR_PLLON;                                                                // PLL inschakelen
    while((RCC->CR & RCC_CR_PLLRDY) == 0);                                  // Wacht tot PLL zeker ingeschakeld is
 
    RCC->CFGR |= RCC_CFGR_SW_PLL;                                                   // PLLCLK selecteren als SYSCLK (48MHz)
    while((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL);  // Wait until the PLL is switched on
         
    RCC->CFGR |= RCC_CFGR_HPRE_DIV1;                                                // SYSCLK niet meer delen, dus HCLK = 48MHz
    RCC->CFGR |= RCC_CFGR_PPRE_DIV1;                                                // HCLK niet meer delen, dus PCLK = 48MHz  
     
    SystemCoreClockUpdate();                                                                // Nieuwe waarde van de core frequentie opslaan in SystemCoreClock variabele
    SysTick_Config(48000);                                                                  // Interrupt genereren. Zie core_cm0.h, om na ieder 1ms een interrupt
                                                                                                                    // te hebben op SysTick_Handler()
}


Greetz Sandeerius

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