The STM32F7 onboard DAC is only 12 bits. I only need mono audio input. Suppose I drive the left ADC input directly and the right from an op amp gain stage of say x16 and then combine the lowest 4 bits of R with left-shifted L? Do I have something akin to a 16 bit ADC? Should I diode-clamp the output of R so I don't generate overages to the ADC?

There could be differential nonlinearity, such that a step from 0x7ff to 0x800 is guaranteed to be not backwards, whereas if you have 0x7ff and add 15/16 of a bit, you could well end up higher than 0x800. (I know this is describing a DAC; the equivalent in an ADC is missing codes).

There could be electrical noise (if the statistics are in your favour you might find that simply summing 16 readings will give you an extra bit or two in useful resolution).

As to your proposed technique, my guess is that for a lot of the time the op-amp output would be saturated and the right ADC would either be reading 0xfff or 0x000. But remember that even when the right ADC is not saturated, there will be some delay / phase-shift / change in frequency-response / gain error through the op-amp. I think you'd do better using the entire right ADC where the reading from the left ADC tells you that the right one isn't saturated, and otherwise use a left-shifted version of the left ADC.

I have used this technique in the past to improve

dynamic rangebut I know that at best I only ever had 12 useful bits of reading. In my case the op-amp ran of the same supply as the stm32 so I did not need to worry about clamping.Hope this helps,

Danish