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STM32L476xx disambiguation

Question asked by Noyb on May 18, 2016
Latest reply on Jan 19, 2017 by Imen D
Hi, currently browsing the doc and the source files provided with MX, I've got some questions regarding the STM32L476RCT6.

The AC6 (SystemWorkbench) Eclipse based project defines STM32L476xx, hence the main include file Drivers\CMSIS\Device\ST\STM32L4xx\Include\stm32l4xx.h includes stm32l476xx.h which differs from the RM0351 documentation (en.DM00083560.pdf) :

http://www.st.com/content/ccc/resource/technical/document/reference_manual/02/35/09/0c/4f/f7/40/03/DM00083560.pdf/files/DM00083560.pdf/jcr:content/translations/en.DM00083560.pdf

Case 1 :

stm32l476xx.h, l3673
#define  DAC_SR_BWST1                        ((uint32_t)0x20008000U)        /*!<DAC channel1 busy writing sample time flag */

en.DM00083560.pdf, p567
17.5.14 DAC status register (DAC_SR)

Could you explain why this is not just 0x00008000U ? Why does it also features the DAC_SR_DMAUDR2 macro ?

Case 2 :

stm32l476xx.h, l483
FIREWALL_TypeDef, RESERVED1 and RESERVED2

stm32l476xx.h, l5377
/*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL;LSSA;LSL register */

What are LSSA and LSL registers ? They are not described into the documentation and referenced in the header file.

Case 3 :

stm32l476xx.h, l855
SDMMC_TypeDef, no RESP0 register

stm32l476xx.h, l7056
/******************  Bit definition for SDMMC_RESP0 register  ******************/

This register is not described into the documentation and referenced in the header file.

Case 4 :

stm32l476xx.h, l943
TIM_TypeDef, no CCMR3 register

stm32l476xx.h, l7851
/******************  Bit definition for TIM_CCMR3 register  *******************/

This register is not described into the documentation and referenced in the header file.

Case 5 :

stm32l476xx.h, l1053
USB_OTG_GlobalTypeDef, HNPTXSTS register

en.DM00083560.pdf, p1541
43.15.11 OTG non-periodic transmit FIFO/queue status register (OTG_HNPTXSTS)

stm32l476xx.h, l9192
/********************  Bit definition for USB_OTG_GNPTXSTS register  ********************/

The GNPTXSTS register is not described into the documentation and referenced in the header file.

Is it the misnamed HNPTXSTS register ?

Case 6 :

stm32l476xx.h, l1053
USB_OTG_GlobalTypeDef, GDFIFOCFG register

This register is not described into the documentation and the header file.

Case 7 :

stm32l476xx.h, l1053
USB_OTG_GlobalTypeDef, GADPCTL register

en.DM00083560.pdf, p1548
43.15.16 OTG ADP timer, control and status register (OTG_GADPCTL)

This register is not described into the the header file.

Case 8 :

stm32l476xx.h, l1049
   __IO uint32_t GADPCTL;             /* ADP Timer, Control and Status Register          60Ch*/

Address should be 060h.

Case 9 :

stm32l476xx.h, l1050
    uint32_t  Reserved43[39];         /* Reserved                                        058h-0FFh*/

Address range is wrong.

Case 10 :

stm32l476xx.h, l1052
  __IO uint32_t DIEPTXF[0x0F];        /* dev Periodic Transmit FIFO */

en.DM00083560.pdf, p1519
Table 256. Core global control and status registers (CSRs) (continued)

The OTG_DIEPTXFx registers are given from 'x = 1..5', address range 0x104 - 0x184 (5 x 0x20) but the array is defined at 0x0F (dec 15) so which one is correct ?

Case 11 :

stm32l476xx.h, l1053
USB_OTG_DeviceTypeDef, DEACHMSK register

This register is not described into the documentation and the header file.

Case 12 :

stm32l476xx.h, l9264
/********************  Bit definition for USB_OTG_DEACHINTMSK register  ********************/

There is no DEACHINTMSK register described into the documentation and referenced in the header file.

Case 13 :

stm32l476xx.h, l1053
USB_OTG_DeviceTypeDef, DINEP1MSK register

This register is not described into the documentation and the header file.

Case 14 :

stm32l476xx.h, l1053
USB_OTG_DeviceTypeDef, DOUTEP1MSK register

This register is not described into the documentation and the header file.

Case 15 :

stm32l476xx.h, l1109
USB_OTG_OUTEndpointTypeDef, DOEPDMA register

This register is not described into the documentation and the header file.

Case 16 :

stm32l476xx.h, l1123
USB_OTG_HostTypeDef, no HPRT register

stm32l476xx.h, l9304
/********************  Bit definition for USB_OTG_HPRT register  ********************/

en.DM00083560.pdf, p1556
43.15.26 OTG Host port control and status register (OTG_HPRT)

This register is not referenced in the header file. Since it is a HOST register, shouldn't it be added to the USB_OTG_HostTypeDef structure ? Like this :

typedef struct
{
  __IO uint32_t HCFG;        /* Host Configuration Register    400h*/
  __IO uint32_t HFIR;        /* Host Frame Interval Register   404h*/
  __IO uint32_t HFNUM;       /* Host Frame Nbr/Frame Remaining 408h*/
  uint32_t Reserved40C;      /* Reserved                       40Ch*/
  __IO uint32_t HPTXSTS;     /* Host Periodic Tx FIFO/ Queue Status 410h*/
  __IO uint32_t HAINT;       /* Host All Channels Interrupt Register 414h*/
  __IO uint32_t HAINTMSK;    /* Host All Channels Interrupt Mask 418h*/
  uint32_t Reserved41C[9];   /* Reserved                       41Ch-43Ch*/
  __IO uint32_t HAINTMSK;    /* Host Port Control And Status Register 440h*/
} USB_OTG_HostTypeDef;

Case 17 :

stm32l476xx.h, l1137
USB_OTG_HostChannelTypeDef, HCDMA register

stm32l476xx.h, l9482
/********************  Bit definition for USB_OTG_HCDMA register  ********************/

This register is not described into the documentation.

Case 18 :

stm32l476xx.h, l9293
/********************  Bit definition for USB_OTG_DIEPEACHMSK1 register  ********************/

There is no DIEPEACHMSK1 register described into the documentation and referenced in the header file.

Case 19 :

stm32l476xx.h, l9330
/********************  Bit definition for USB_OTG_DOEPEACHMSK1 register  ********************/

There is no DOEPEACHMSK1 register described into the documentation and referenced in the header file.

Case 20 :

stm32l476xx.h, l8904
/********************  Bit definition for USB_OTG_PCGCR register  ********************/

en.DM00083560.pdf, p1522
Table 260. Power and clock gating control and status registers

There is no PCGCR register described into the documentation and referenced in the header file.

However, regarding its address range (0xE00-0xE04) it looks like it might be the PCGCCTL register :

stm32l476xx.h, l1314
#define USB_OTG_PCGCCTL_BASE                 ((uint32_t)0x00000E00U)

stm32l476xx.h, l9526
/********************  Bit definition for PCGCCTL register  ********************/

en.DM00083560.pdf, p1585
43.15.53 OTG power and clock gating control register (OTG_PCGCCTL)

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