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DMA latency by fast ADC acquisition.

Question asked by go.eric on May 10, 2016
Latest reply on May 11, 2016 by go.eric
Hi there,

Im currently running into a problem with a stm32F334C8Tx controller.
The following data represent my program configuration.


- Clock 72MHz

- 12Bits
- Sync Clock mode PRESCALE 1 ( 72MHz)
- 4 Regular Channels  ( fast channels  ADC1_AN1 -> ADC2_AN4), AN2 has an offset of 2050, no offset for the others
- No injected channels ( disabled)
- Sampling time 1.5cycles
- Acquisition Time 12.5 cycles
- Total Sampling rate 1.28MS/s/channel
- Scan mode enabled
- Continuous conversion enabled
- Overrun Data overwritten
- DMA continuous Request enabled
- No Interrupt enabled

DMA used with ADC:
- Channel 1
- Circular Mode
- Priority: high  (higher as other DMA channels)
- Interrupt Enabled ( Error, Half Transfer and Tranfer Complete)
- Buffer Size : uint16_t [1030]

- In Parralel:
- UART3 RX and TX are operating ( on a "On Demand basis"), using DMA channels 2 and 3 ( lower priority)
- The FPU is used during the DMA Interrupt to calculate RMS values of the Acquired ones.

The Conversion is started once at the start of the device, and keeps acquiring data continuously.
The Buffer is use in a Ping-Pong way, data being used at each interrupt of the DMA Channel ( first
516 uints for HT interrupt , last 516 uints for the TC interrupt and so on)

The ADC is used to measure several signals based on a System running at up to 200kHz.

Our friend Niyquist states that i thus need at least 400KHz as min sampling frequency,
which would be met with the 1.28MS/s/Channel sampling rate.

In normal Case , the data Structure in the Buffer should look like the following
with N being a natural integer ( N is function of my buffer size)
BUF[N + 0] = Val[Channel1_N]
BUF[N + 1] = Val[Channel2_N]
BUF[N + 2] = Val[Channel3_N]
BUF[N + 3] = Val[Channel4_N]

However there seem to be troubles in the data transfers from the ADC to DMA buffer during the operations,
as in some cases, there appears to be an offset introduced intto my buffer, being such that the buffer could look like the 3 following cases:
BUF[N + 0] = Val[Channel2_N] or Val[Channel3_N] or Val[Channel4_N]
BUF[N + 1] = Val[Channel3_N] or Val[Channel4_N] or Val[Channel1_N]
BUF[N + 2] = Val[Channel4_N] or Val[Channel1_N] or Val[Channel2_N]
BUF[N + 3] = Val[Channel1_N] or Val[Channel2_N] or Val[Channel_3N]

The most easy explanation would be that the DMA being busy , another conversion occurs in the ADC before the data has been moved to the memory location,
offseting the full future set of acquired datas from 1 or several steps into the buffer, and making the acquisition useless.
I suspect a timing problem too, maybe caused by the Round Robin priority scheme described in the AN4031- DMA controller description for access to the SRAM, though that
application note doesn't seem to apply directly to the STM32F3 but rather to F2 and F4 series.

As i'm not yet that deep into the Cortex M4 architecture, I was wondering if anybody has enough knowledge to enlight me on what could be happening into my processor, and if there is a work around or a fix to that problem.

All help is welcome.