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What is ocurrance and effect of Dyn/Static bank switch errata STM32F429?

Question asked by jordan.graham on Mar 25, 2016
Latest reply on Mar 28, 2016 by jordan.graham

We are using STM32F429IIT6. We have IC revision 1. Looking at latest errata (Rev 9), seems that the following applies:
2.9.7 FMC dynamic and static bank switching
The dynamic and static banks cannot be accessed concurrently.

How and when does this occur? How does the issue manifest itself? What does it mean to access 'concurrently'?

We have SDRAM (16-bit wide) and LCDs (accessed as SRAM, using 32-bit data bus, only use writes), interfaced using the FMC on different banks (initialized using the STM32F4xx HAL).  Is this a situation where this errata would occur?

We can access the SDRAM fine. Can write to the LCDs fine. Can use the SDRAM and write to LCDs in the same application fine in some situations (e.g. loop that does 16-bit reads of SDRAM, to compose next data writes to LCDs - so SDRAM and LCD read/writes are interleaves with some data manipulation in between). Other situations get strange data written to LCDs - such as when doing loop of 'fast' 32-bit read of SDRAM that is then written to the LCD. Doing an 'almost as fast' loop of 2x16-bit reads of SDRAM, compose that into 32bit, then write to LCD... this shows a bit of corruption of data. The code accessing the SDRAM and LCDs is linear procedure.

Checking other errata, they don't appear to be issues. e.g. "2.9.5 Interruption of CPU read burst access to an end of SDRAM row" - the workaround is already.