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Confused by STM32L4 datasheet max SPI clock frequencies

Question asked by haun.mark.001 on Mar 22, 2016
Latest reply on Mar 23, 2016 by haun.mark.001
I'd like to use an STM32L4 in a project where I am interfacing with a 1-MSPS, 16-bit SPI ADC (LTC2378-16).  Obviously the SPI clock has to be > 16 MHz to run this at full speed.  However, for best performance the clocking out of each sample should be restricted to ~ half of the overall sample period.  Thus, I really need to run SPI close to the theoretical maximum of 40 MHz.

The reference manual doesn't say much about clock speeds.  The master-mode clock control has a setting for PCLK/2 which would allow 40 MHz with the max APBx clock of 80 MHz.  But the datasheet paints a more complex picture:

It lists a top speed of 40 MHz for "master transmitter" or "slave receiver."  For "master receive / full duplex" it says the max is 13 or 24 MHz depending on supply voltage.  Does anyone know why the max reception speed would be different in master vs slave modes?  I initially thought receive might be slower due to synchronizers on the input pins, but that doesn't explain why master receive and slave receive would be different.

If I have to, I could probably figure out a complicated timer setup to generate exactly 16 clocks after every ADC READY indication, pipe that clock into both the ADC and SPI_CK, and run the SPI peripheral in slave mode.  I just don't see why that should allow me almost 2x the speed vs. having the SPI peripheral generate the clock itself in master mode.  I mean, everything is basically the same in those two scenarios, except where the clock gets generated.

Anyone have more insight?  Is the datasheet really correct?