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STM32F4 SPI management

Question asked by Gerardo Gallucci Employee on Mar 10, 2016
Latest reply on Mar 11, 2016 by Gerardo Gallucci
Hi all,

what's the best way to manage a full-duplex SPI slave interface, running on STM32F4 + RTOS?
I tried 3 different strategies, but none of them seem suitable for high performance.

What I have:
- 5 pins SPI: miso mosi clk cs irq
- 2x DMA: Tx (normal?) and Rx (circular?)
- 2x Buffers: Tx and Rx
- Interrupts on SPI (TXE, RXNE, ...), DMA (TC, HT, ...)
- 2x Tasks: ParseRxBuffer, ParseTxBuffer
- queues, semaphores, etc...

q1: chip select in HW or in SW? (I think in HW)
q2: even if working in HW, should interrupt be used for CS line? (I think so)
q3: can I use HW CS and interrupt on that line? (I hope so)

I think DMA on RX should be always running, while DMA on TX should be enabled only when needed

q4: which event should be used to wake RxBufferParserTask? Since there is no "idle interrupt" on SPI peripheral. (I think: interrupt on CS line). I tried RXNE interrupt, but leads to stop&start DMA on RX. Not so good. I heard also about timers on clock line...

I expect, during TX, sending dummy data (0xFF) while nothing needs to be sent (SPI Master put CS low). I expect also sending TX buffer if something needs to be sent (IRQ line put low).

q5: can I change "on the fly" TX DMA buffer content, if a transmission is needed while CS line is already low?

Thanks for knowledge sharing :-)

ps: both frames (Master to Slave, and slave to Master) start with an header containing frame length...